1. Field of the Invention
The present invention relates to a testing apparatus and method of testing operation timing of a semiconductor device. In particular, the present invention relates to a testing apparatus and method which perform a circuit simulation using parameters to check operation timing of a semiconductor device and test operation timing of the semiconductor device using a result of the circuit simulation.
2. Description of Related Art
With advances of the semiconductor wafer process technology and the circuit technology, the operation speeds of large-capacity semiconductor devices are becoming higher increasingly. In this connection, the technology of testing such devices, in particular, the technology of measuring operation timing such as an access time of a high-speed device with high accuracy, is becoming important.
Conventionally, as for high-accuracy access time measurement, not only is a subject device (hereinafter referred to as xe2x80x9cDUTxe2x80x9d) measured with a tester but also the following measure is taken. Electrical characteristics of a measurement jig, the driver and the comparator of a tester, and the output buffer circuit of the DUT are modeled. An electrical characteristic simulation is performed in advance with Spice (a circuit simulator), for example, by using the modeled electrical characteristics. Operation timing obtained as a simulation result is compared with operation timing as a result of an actual measurement on the DUT, to increase the measurement accuracy.
Specifically, a reason for a difference between a circuit simulation value and an actual measurement value is investigated, influences of the reason are recognized quantitatively, and problems of the measurement system are improved.
Conventionally, since an operation timing of a semiconductor device is judged in the above-described manner, the characteristics of the output buffer transistor of a DUT tend to be influenced more by a wafer process variation as the operation speed of the DUT increases, which is a factor in causing a difference between a circuit simulation result and a DUT actual measurement value. A largest factor in causing such a difference is thought to be employing, as characteristics of the output buffer circuit of a DUT that is incorporated in a circuit simulation, transistor parameters obtained by measuring a wafer of a different lot from the lot of the DUT. Where timing measurement on a DUT and measurement of transistor parameters to be used for a circuit simulation are performed separately, the circuit simulation may not be accurate enough to cover the actual measurement. As a result, there may occur a case that erroneous Spice transistor parameters (due to a difference between wafer process lots) are used as they are in the circuit simulation, to produce an erroneous measurement result. It is expected that such an error will become more noticeable as the operation speed of a device increases.
The present invention has been achieved in view of the above problems, and an object of the invention is therefore to provide a testing apparatus and method which can easily measure and evaluate, on a tester, transistor characteristics of a wafer of the same lot or wafer as the lot or wafer of a DUT to obtain transistor parameters for a Spice circuit simulation and which can prevent an error of the above kind by measuring high-speed operation timing of the DUT using the transistor parameters thus obtained.
According to a first aspect of the present invention, there is provided a testing apparatus for measuring operation timing of a semiconductor device, comprising: measuring means for measuring transistor characteristics of a circuit for transistor characteristics extraction that is formed in advance and belongs to the same lot or wafer as a lot or wafer of a subject semiconductor device; storage means for storing measurement values of the measuring means as parameters; circuit simulation means for performing a circuit simulation on a measurement system using the parameters stored in the storage means, and for storing resulting operation timing in the storage means; actual measurement means for actually measuring operation timing of the subject semiconductor device, and for comparing a resulting actual measurement value with the operation timing that is obtained by the circuit simulation and is stored in the storage means; and a CPU for controlling the measuring means, the storage means, the circuit simulation means, and the actual measurement means.
According to a second aspect of the present invention, there is provided a testing method of measuring operation timing of a semiconductor device, wherein a difference between an actual measurement value of operation timing of a subject semiconductor device and operation timing obtained by a circuit simulation is detected by the testing apparatus according to the present testing apparatus of claim 1 or 2.
According to a third aspect of the present invention, there is provided a testing method of measuring operation timing of a semiconductor device, comprising the steps of: measuring transistor characteristics of a circuit for transistor characteristics extraction that was formed in advance and belongs to the same lot or wafer as a lot or wafer of a subject semiconductor device; storing measurement values of the transistor characteristics as parameters; performing a circuit simulation on a measurement system using the parameters, and storing resulting operation timing; and actually measuring operation timing of the subject semiconductor device, comparing a resulting actual measurement value with the operation timing that was obtained by the circuit simulation, and modifying a test program for operation timing measurement when the difference between the actual measurement value of the operation timing of the subject semiconductor device and the operation timing obtained by the circuit simulation is greater than or equal to a predetermined value.